minute0.vhd

来自「这是一个数字中的课程设计」· VHDL 代码 · 共 42 行

LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY minute0 IS
   PORT(
		en       	: IN	STD_LOGIC;
        min1,min0   :out std_logic_vector(3 downto 0);
		co			: OUT	STD_LOGIC);
END minute0;
ARCHITECTURE art OF minute0 IS
BEGIN
  Process (en)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
     if en'event and en='1' then
        if cnt1="0101"and cnt0="1001"then
           co<='1';
          cnt1:="0000";
         cnt0:="0000";
        elsif cnt0<"1001"then
            cnt0:=cnt0+1;
 			co<='0';
        else
            cnt0:="0000";
     		if cnt1<"0101"then
               cnt1:=cnt1+1;
				co<='0';
            else
               cnt1:="0000";
     			co<='0';
            end if;
          end if;
      min1<=cnt1;
      min0<=cnt0;
     end if;
    end process;
	end art;