📄 main.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity main is
port(clk1:in std_logic;
leda1,leda10a,ledb1,ledb10b:out std_logic_vector(0 to 3);
red1,red2,green1,green2,yellow1,yellow2:out std_logic);
end main;
architecture stl of main is
component jtdmain
port(clk:in std_logic;
kjs1,kjs10a:out std_logic_vector(0 to 3);
s1,s2:out std_logic );
end component;
component js
port(clk:in std_logic;
led1,led10a:out std_logic_vector(0 to 3));
end component;
component xs
port(s,clk:in std_logic;
js1,js10a:in std_logic_vector(0 to 3);
r,g,y:out std_logic);
end component ;
signal bb1,bb2: std_logic;
signal aa1,aa2: std_logic_vector(0 to 3);
begin
u1:jtdmain port map(clk1,aa1,aa2,bb1,bb2);
u2:xs port map(bb1,clk1,aa1,aa2,red1,green1,yellow1);
u3:xs port map(bb2,clk1,aa1,aa2,red2,green2,yellow2);
u4:js port map(clk1,leda1,leda10a);
u5:js port map(clk1,ledb1,ledb10b);
end stl;
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