代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/392144/8361248
vhd sine.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine is
port(
clk:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end entity sine;
architecture
www.eeworm.com/read/292193/8367724
vhd encdec_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b and dec_8b10b
-- Design : 8b-10b Encoder/Decoder Test Bench
-- Project : 8000
www.eeworm.com/read/292193/8367732
vhd enc_8b10b_tb.vhd
-------------------------------------------------------------------------------
--
-- Title : Test Bench for enc_8b10b
-- Design : 8b/10b Encoder Test Bench
-- Project : 8000 - 8b10b_encdec
-- Au
www.eeworm.com/read/291905/8388520
vhd pre_norm_fmul_arch.vhd
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_misc.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY pre_norm_fmul IS
PORT(
clk : IN std_logic ;
fpu_op : IN
www.eeworm.com/read/391620/8394665
vhd tabletennis.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY tabletennis IS
PORT(clk,p1,p2,reset,speed_sel,first_sel,judge: IN STD_LOGIC;
led: OUT STD_LOGIC_
www.eeworm.com/read/192199/8399720
vhd seven.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY seven IS
PORT
( men: IN std_logic_vector(6 downto 0);
pass: buffer std_logic
);
END seven;
ARCHITECTURE beha
www.eeworm.com/read/391516/8399759
txt shizhong.txt
1. 10进制计数器设计与仿真
（1）10进制计数器VHDL程序
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.
www.eeworm.com/read/391511/8399851
txt dianziqin.txt
1.顶层程序与仿真
（1）顶层VHDL程序
--文件名：top.vhd
--功能：顶层文件
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port
www.eeworm.com/read/391317/8409688
vhd saomiao.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiao is
port(one,ten:in std_logic_vector(3 downto 0);
clk:in std_logic;---1khz;
data:out
www.eeworm.com/read/291438/8420277
vhd cnt10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk: in std_logic;
cout: out std_logic);
end cnt10;
architecture behav of cnt10 is
begin