saomiao.vhd

vhdl的铜须等

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity saomiao is 
port(one,ten:in  std_logic_vector(3 downto 0);
         clk:in  std_logic;---1khz;
        data:out std_logic_vector(3 downto 0);
         adr:out std_logic_vector(1 downto 0));
end saomiao;
architecture one of saomiao is
signal cnt: std_logic_vector(1 downto 0);
signal    d: std_logic_vector(3 downto 0);
begin
  process(clk)
    begin
      if(clk 'event and clk='1')then
         if(cnt="01")then
            cnt<="00";
         else
            cnt<=cnt +1;
         end if;
      end if;
end process;
  process(cnt,one,ten)
    begin
      case cnt is
           when "00"=>d<=one;adr<="01";
           when "01"=>d<=ten;adr<="10";
           when others=>null;
      end case;
     data<=d;
  end process;
end one;