shizhong.txt

这个VHDL与其他上传的代码不同

1. 10进制计数器设计与仿真
（1）10进制计数器VHDL程序
--文件名：counter10.vhd。
--功能：10进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter10 is
    Port ( clk : in std_logic;
          reset : in std_logic;
          din : in std_logic_vector(3 downto 0);
          dout : out std_logic_vector(3 downto 0);
		  c:out std_logic);
end counter10;
architecture Behavioral of counter10 is
   signal count : std_logic_vector(3 downto 0);
begin
    dout <= count;
	process(clk,reset,din)
	begin
	   if reset='0'then
		 count <= din ;
		 c<='0';
       elsif rising_edge(clk) then
		   if count = "1001" then
			   count <= "0000";
			   c<='1';
           else 
			   count <= count+1;
			   c<='0';
           end if;
      end if;
    end process;
end Behavioral;
（2）	10进制计数器仿真
 
2. 6进制计数器设计与仿真
（1）6进制计数器VHDL程序
--文件名：counter6.vhd。
--功能：6进制计数器，有进位C
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter6 is
    Port ( clk : in std_logic;
         reset : in std_logic;
         din : in std_logic_vector(2 downto 0);
         dout : out std_logic_vector(2 downto 0);
		 c:out std_logic);
end counter6;
architecture Behavioral of counter6 is
signal count : std_logic_vector(2 downto 0);
begin
    dout <= count;
	process(clk,reset,din)
	begin
	   if reset= '0' then
		  count <= din;
		  c<='0';
       elsif rising_edge(clk) then
		   if count="101" then
			   count<="000";
			   c<='1';
           else
			   count<=count+1;
			   c<='0';
          end if;
      end if;	
   end process;
end Behavioral;
（2）6进制计数器仿真
 
3. 6进制计数器设计与仿真
（1）24进制计数器VHDL程序
--文件名：counter24.vhd。
--功能：24进制计数器。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter24 is
    Port ( clk : in std_logic;
         reset : in std_logic;
         din : in std_logic_vector(5 downto 0);
         dout : out std_logic_vector(5 downto 0));
end counter24;
architecture Behavioral of counter24 is
signal count : std_logic_vector(5 downto 0);
begin
    dout <= count;
	process(clk,reset,din)
	begin
	   if reset= '0' then
		   count <= din;
       elsif rising_edge(clk) then	   
		   if count(3 downto 0)="1001" then
			 count(3 downto 0)<="0000";
			count(5 downto 4)<=count(5 downto 4) +1;
         else
			count(3 downto 0)<=count(3 downto 0)+1;
         end if;
		 if count="100011" then
		   count<="000000";
         end if;
      end if;
   end process;
end Behavioral;
（2）24进制计数器仿真
 
4. 译码器设计
（1）译码器VHDL程序
--文件名：decoder.vhd。
--功能：将4bit二进制数译码，在LED上显示相应数字。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (din:in std_logic_vector(3 downto 0 );   --四位二进制码输入
dout:out std_logic_vector(6 downto 0) );  --输出LED七段码
end decoder;
architecture Behavioral of decoder is
begin
process(din)
begin
case din is
when "0000" => dout<="0000001";--0
when "0001" => dout<="1001111";--1
when "0010" => dout<="0010010";--2
when "0011" => dout<="0000110";--3
when "0100" => dout<="1001100"; --4
when "0101" => dout<="0100100";--5
when "0110" => dout<="0100000";--6
when "0111" => dout<="0001111";--7
when "1000" => dout<="0000000";--8
when "1001" => dout<="0000100";--9
when others => dout<="1111111";
end case;
end process;
end Behavioral;
5. 顶层设计与仿真
（1）顶层设计VHDL程序
--文件名：clock.vhd。
--功能：时钟的顶层设计。
--最后修改日期：2004.3.20
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clock is
    Port ( clk : in std_logic;                 --1Hz
         reset : in std_logic;                --复位信号
         dins : in std_logic_vector(6 downto 0);--秒钟预置
         dinm : in std_logic_vector(6 downto 0);--分钟预置
         dinh : in std_logic_vector(5 downto 0);--时钟预置
		 secondl: out std_logic_vector(6 downto 0);--秒钟低位输出
		 secondh: out std_logic_vector(6 downto 0); --秒钟高位输出
		 minutel: out std_logic_vector(6 downto 0); --分钟低位输出
		 minuteh: out std_logic_vector(6 downto 0); --分钟高位输出
		 hourl: out std_logic_vector(6 downto 0); --小时低位输出
		 hourh: out std_logic_vector(6 downto 0)); --小时高位输出
end clock;
architecture Behavioral of clock is
   component counter10 is
	Port ( clk : in std_logic;
         reset : in std_logic;
         din : in std_logic_vector(3 downto 0);
         dout : out std_logic_vector(3 downto 0);
		 c:out std_logic);
end component;

	component counter6 is
	Port ( clk : in std_logic;
         reset : in std_logic;
         din : in std_logic_vector(2 downto 0);
         dout : out std_logic_vector(2 downto 0);
		 c:out std_logic);
	end component;

	component counter24 is
	 Port ( clk : in std_logic;
          reset : in std_logic;
          din : in std_logic_vector(5 downto 0);
          dout : out std_logic_vector(5 downto 0));
	end component;

	component decoder is
	Port (din:in std_logic_vector(3 downto 0 );   
         dout:out std_logic_vector(6 downto 0));  
	end component;

	signal c1,c2,c3,c4:std_logic;
	signal doutsl,doutml:std_logic_vector(3 downto 0);
	signal doutsh,doutmh:std_logic_vector(2 downto 0);
	signal douth:std_logic_vector(5 downto 0);
	signal rdoutsh,rdoutmh:std_logic_vector(3 downto 0); 
	signal rdouth:std_logic_vector(7 downto 0);
begin
	rdoutsh <= '0'&doutsh;   --将秒钟高位数据变为4位，再进行译码
	rdoutmh <= '0'&doutmh;  --将分钟高位数据变为4位，再进行译码
	rdouth <="00"&douth;   --将时钟高位数据变为4位，再进行译码
	u1: counter10 port map( clk=>clk,reset=>reset,
	                    din=>dins(3 downto 0),
						dout=>doutsl,
						c=>c1);
   u2: counter6 port map( clk=>c1,reset=>reset,
	                  din=>dins(6 downto 4),
					  dout=>doutsh,
					  c=>c2);
   u3: counter10 port map(	clk=>c2,reset=>reset,
	                    din=>dinm(3 downto 0),
						dout=>doutml,
						c=>c3);
   u4: counter6 port map( clk=>c3,reset=>reset,
	                       din=>dinm(6 downto 4),
						   dout=>doutmh,
						   c=>c4);
	u5: counter24 port map( clk=>c4,reset=>reset,
	                       din=>dinh,
								  dout=>douth);
    u6: decoder port map( din => doutsl,dout => secondl);	 --秒的低位
	u7: decoder port map( din => rdoutsh,dout => secondh); --秒的高位
	u8: decoder port map( din => doutml,dout => minutel);  --分的低位					  
	u9: decoder port map( din => rdoutmh,dout => minuteh); --分的高位
	u10: decoder port map( din => rdouth(3 downto 0),dout => hourh);--时的低位
	u11: decoder port map( din => rdouth(7 downto 4),dout => hourl);--时的高位
end Behavioral;
（2）顶层设计仿真