tabletennis.vhd

游戏代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY tabletennis IS
	PORT(clk,p1,p2,reset,speed_sel,first_sel,judge:	IN STD_LOGIC;
		 			   				led:	OUT STD_LOGIC_VECTOR(7 downto 0);
					   				cat:	OUT STD_LOGIC_VECTOR(5 downto 0);
				     				digit:	OUT STD_LOGIC_VECTOR(6 downto 0));
END ENTITY;

ARCHITECTURE main OF tabletennis IS
SIGNAL clk_temp,p1win,p2win,who,first,p1total,p2total,clear,ends: STD_LOGIC;
SIGNAL score1,score2  : integer range 0 to 11;
SIGNAL total1,total2  : integer range 0 to 4;
SIGNAL total:integer range 0 to 7;

COMPONENT clk_div IS
	PORT(clk,sel:			 IN STD_LOGIC;
		 clk_out:OUT STD_LOGIC);
END COMPONENT;

COMPONENT control IS
	PORT(clk,p1,p2,judge,who,sel,reset:  IN STD_LOGIC;
		  score1,score2:  IN integer range 0 to 11;--当前局比分
			total: IN integer range 0 to 7;
     p1total,p2total,p1win,p2win,clear,first: OUT STD_LOGIC;
			led_out: OUT STD_LOGIC_VECTOR(7 downto 0));--发光二极管的显示
END COMPONENT;

COMPONENT score_stat IS
	PORT(p1win,p2win,reset,reset_all: 	 IN STD_LOGIC;
		 	 score1,score2:	    OUT integer range 0 to 11);
END COMPONENT;

COMPONENT total_stat IS
	PORT(p1total,p2total,reset,ends,reset_all: 	 IN STD_LOGIC;
		 	 total1,total2:	    OUT integer range 0 to 4);
END COMPONENT;

COMPONENT change IS
	PORT(first:IN STD_LOGIC;
		 score1,score2:	IN integer range 0 to 11;
		 total1,total2: IN integer range 0 to 4;
		 total: OUT integer range 0 to 7;
		 ends,who:OUT STD_LOGIC);
END COMPONENT;

COMPONENT score_show IS
	PORT(clk:			IN STD_LOGIC;
		 score1,score2: IN integer range 0 to 11;
		 total1,total2: IN integer range 0 to 4;
		           cat:OUT STD_LOGIC_VECTOR(5 downto 0);
				 digit:OUT STD_LOGIC_VECTOR(6 downto 0));
END COMPONENT;

BEGIN
	U1: clk_div PORT MAP(clk => clk,clk_out => clk_temp,sel=>speed_sel);
	U2: control PORT MAP(clk => clk_temp,p1 => p1,p2 => p2,judge=>judge,reset => reset,who=>who,first=>first,sel=>first_sel,clear=>clear,score1 => score1,score2=>score2,p1win=>p1win,p2win=>p2win,p1total=>p1total,p2total=>p2total,led_out=>led,total=>total);
	U3: score_stat PORT MAP(p1win=>p1win,p2win=>p2win,reset=>clear,reset_all=>reset,score1=>score1,score2=>score2);
	U4: total_stat PORT MAP(p1total=>p1total,p2total=>p2total,total1=>total1,total2=>total2,reset=>clear,reset_all=>reset,ends=>ends);
	U5: change	PORT MAP(first=>first,score1=>score1,score2=>score2,total1=>total1,total2=>total2,ends=>ends,total=>total,who=>who);
	U6: score_show PORT MAP(clk=>clk,score1=>score1,score2=>score2,total1=>total1,total2=>total2,cat=>cat,digit=>digit); 
END ARCHITECTURE;