seven.vhd

seven.vhd 七人表决器VHDL源码 七人表决器.doc 程序说明

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY seven IS
PORT
( men: IN std_logic_vector(6 downto 0);
pass: buffer std_logic
);
END seven;
ARCHITECTURE behave OF seven IS
BEGIN
--stop<=not pass;
PROCESS (men)
variable temp:std_logic_vector(2 downto 0);
BEGIN
temp:="000";
for i in 0 to 6 loop
if(men(i)='1') then
temp:=temp+1;
else
temp:=temp+0;
end if;
end loop;
pass<=temp(2);
--stop<=not(pass);
END PROCESS;
END behave;