代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/220401/14801833
vhd bijiaoqi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bijiaoqi IS
port(a1,a2,b1,b2: in std_logic;
m: out std_logic);
end entity bijiaoqi;
architecture fm1 of bijiaoqi is
signal zdf1,zdf2: s
www.eeworm.com/read/220401/14801835
vhd fenpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk:in std_logic;
outp0,outp1:out std_logic);
end fenpin;
architecture bh of fenpin is
www.eeworm.com/read/220401/14801837
vhd jiafaqi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY jiafaqi IS
port(a: in std_logic;
o1,o2: out std_logic);
end entity jiafaqi;
architecture fh1 of jiafaqi is
begin
o1
www.eeworm.com/read/219216/14891760
vhd pre.vhd
--
-- pre.vhd
--
-- Cordic pre-processing block
--
--
-- step 1: determine quadrant and generate absolute value of X and Y
-- Q1: Xnegative
-- Q2: Ynegative
--
-- step 2: swap X and Y values if Y>X
www.eeworm.com/read/117979/14891798
vhd alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY ALU IS
PORT(
s1,s0: in std_logic;
a: in std_logic_vector(7 downto 0);
b
www.eeworm.com/read/117978/14892225
vhd alu.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY ALU IS
PORT(
s1,s0: in std_logic;
a: in std_logic_vector(7 downto 0);
b
www.eeworm.com/read/218836/14904706
vhd six choose one.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m6_1scan is
port(
reset : in std_logic;
clkscan : in st
www.eeworm.com/read/218217/14930943
vhd common.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS C
www.eeworm.com/read/218217/14930949
vhd vga.vhd
--------------------------------------------------------------------
-- Company : XESS Corp.
-- Engineer : Dave Vanden Bout
-- Creation Date : 05/17/2005
-- Copyright : 2005, XESS C
www.eeworm.com/read/218217/14930953
vhd sdramcntl.vhd
library IEEE, UNISIM;
use IEEE.std_logic_1164.all;
package sdram is
-- SDRAM controller
component sdramCntl
generic(
FREQ : natural := 50_000; -- operating