bijiaoqi.vhd

来自「应用vhdl语言进行加法器的设计」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY bijiaoqi IS
 port(a1,a2,b1,b2: in std_logic;
      m: out std_logic);
end entity bijiaoqi;
architecture fm1 of bijiaoqi is
 signal zdf1,zdf2: std_logic; 
 begin
 process(a1,a2,b1,b2)
 begin
 zdf1 <=a1 xor b1; 
 zdf2 <=a2 xor b2;
 if zdf1='0' and zdf2='0'then
    m<=not zdf1;
  else m<='0'; 
 end if;
end process;
end architecture fm1;