six choose one.vhd

来自「last time when i came here to find some 」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity m6_1scan is
  port(
    reset                        : in  std_logic;
    clkscan                      : in  std_logic;
    in1, in2, in3, in4, in5, in6 : in  std_logic_vector(3 downto 0);
    data                         : out std_logic_vector(3 downto 0);
    sel                          : out std_logic_vector(2 downto 0));  
end m6_1scan;
architecture rt1 of m6_1scan is
  signal count : std_logic_vector(2 downto 0);
begin
  process(clkscan, reset)
  begin
      if reset = '1' then
      count <= "000";
    elsif(clkscan = '1'and clkscan'event) then
      if count = "101" then
        count <= "000";
      else
        count <= count+1;
      end if;
    end if;
  end process;
  sel <= count;

  process(count,in1,in2,in3,in4,in5,in6)
    begin
case count is
    when "000"  => data <= in1;
    when "001"  => data <= in2;
    when "010"  => data <= in3;
    when "011"  => data <= in4;
    when "100"  => data <= in5;
    when others => data <= in6;
  end case;
end process;
end rt1;