fenpin.vhd

应用vhdl语言进行加法器的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is 
 port(clk:in std_logic;
      outp0,outp1:out std_logic);
end fenpin;
architecture bh of fenpin is
begin 
 process(clk)
  variable sum:std_logic_vector(2 downto 0);
  begin 
    if rising_edge(clk) then
         sum :=sum+'1';
         outp0 <=sum(0);
         outp1 <=sum(1);
       if sum=4 then 
          sum:="000";   
       end if;
    end if;
end process;
end bh;