jiafaqi.vhd

来自「应用vhdl语言进行加法器的设计」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY jiafaqi IS
 port(a: in std_logic;
     o1,o2: out std_logic);
end entity jiafaqi;
architecture fh1 of jiafaqi is
 begin
 o1<=(a or a) AND(a NAND a);
 o2<=NOT(a NAND a);
end architecture fh1;