代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/404317/11487655
vhd div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity div is
port(clk:in std_logic; --clk:1MHZ
y:buffer std_logic); -- y:1M/2000=500HZ
end div;
arch
www.eeworm.com/read/404187/11490600
cmp t32.cmp
-- Generated by PCI Compiler 3.2.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-
www.eeworm.com/read/403676/11513059
vhd seven_seg_pio.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
www.eeworm.com/read/403333/11518840
vhd etester.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY etester IS
PORT (
BCLK : IN STD_LOGIC; --标准频率时钟信号clock2，50MHZ
TCLK : IN STD_LOGIC; --待测频率时钟信号
www.eeworm.com/read/403310/11519307
vhd reg4.vhd
--REG4.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4 IS
PORT(D:IN STD_LOGIC_VECTOR(3 TO 0);
EN,CLK:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 TO 0));
END ENTITY REG4;
www.eeworm.com/read/403298/11519548
vhd piso.vhd
library ieee;
use ieee.std_logic_1164.All;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sclk,sl : IN std_logic;
q: OUT STD_LOGIC);
END piso;
ARCHITECTURE
www.eeworm.com/read/403298/11519582
vhd piso.vhd
library ieee;
use ieee.std_logic_1164.All;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sclk,sl : IN std_logic;
q: OUT STD_LOGIC);
END piso;
ARCHITECTURE
www.eeworm.com/read/403296/11519633
vhd piso.vhd
library ieee;
use ieee.std_logic_1164.All;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY piso IS
PORT(data :IN std_logic_vector(9 DOWNTO 0);
sl,sclk : IN
www.eeworm.com/read/402992/11525053
vhd ch4_6_1.vhd
-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--*************************************
www.eeworm.com/read/402992/11525063
vhd ch4_4_1.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY CH4_4_1 IS
PORT ( A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK: IN STD_LOGIC;
RST: IN STD_LOG