ch4_6_1.vhd

《VHDL与数字电路设计》配套光盘,可以实际调用

-- ********************************************
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--*********************************************
ENTITY Ch4_6_1 is
	PORT(
		 DATAOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --Data Output  	
		 ADDR    : IN  STD_LOGIC_VECTOR(3 DOWNTO 0); --ADDRESS						 --ROM ADDRESS 		
		 CE		 : IN  STD_LOGIC					-- Chip Enable		
		);
END Ch4_6_1;

--*********************************************
ARCHITECTURE a OF Ch4_6_1 IS
BEGIN
	DATAOUT <= "00001001" WHEN ADDR = "0000" AND CE='0' ELSE
			   "00011010" WHEN ADDR = "0001" AND CE='0' ELSE
			   "00011011" WHEN ADDR = "0010" AND CE='0' ELSE
			   "00101100" WHEN ADDR = "0011" AND CE='0' ELSE
			   "11100000" WHEN ADDR = "0100" AND CE='0' ELSE
			   "11110000" WHEN ADDR = "0101" AND CE='0' ELSE
			   "00010000" WHEN ADDR = "1001" AND CE='0' ELSE
			   "00010100" WHEN ADDR = "1010" AND CE='0' ELSE
			   "00011000" WHEN ADDR = "1011" AND CE='0' ELSE
			   "00100000" WHEN ADDR = "1100" AND CE='0' ELSE
			   "xxxxxxxx";
--"00000000";		 
END a;