reg4.vhd

来自「8位加法器VHDL源程序」· VHDL 代码 · 共 21 行

--REG4.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG4 IS 
  PORT(D:IN STD_LOGIC_VECTOR(3 TO 0);
      EN,CLK:IN STD_LOGIC;
       Q:OUT STD_LOGIC_VECTOR(3 TO 0));
END ENTITY REG4;
ARCHITECTURE ART OF REG4 IS
  BEGIN
  PROCESS(CLK) IS
    BEGIN   
    IF (CLK'EVENT AND CLK='1') THEN
    IF EN='1' THEN 
       Q<=D;
    END IF;
    END IF;
  END PROCESS;
END ARCHITECTURE ART;