代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/245646/12785511
vhd a8255.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR
www.eeworm.com/read/331968/12790240
vhd dff89.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff89 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTO
www.eeworm.com/read/331968/12790260
vhd dff15.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff15 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
Dout : OUT STD_LOGIC_VECT
www.eeworm.com/read/331968/12790597
vhd dff8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dff8 IS
PORT( clk : IN STD_LOGIC;
clear : IN STD_LOGIC;
Din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Dout : OUT STD_LOGIC_V
www.eeworm.com/read/143986/12825166
vhd s8250.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY s8250 IS
PORT(clk, rclk, reset, sin, rd, wr, cs, a2, a1, a0, dsr: IN STD_U
www.eeworm.com/read/244166/12879928
vhd dac2adc.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC2ADC IS
PORT ( CLK : IN STD_LOGIC; --计数器时钟
LM311 : IN STD_LOGIC; --LM311输出，由PIO37口进入FPG
www.eeworm.com/read/143194/12890100
vhd reg.vhd
-- reg.vhd
-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. T
www.eeworm.com/read/143194/12890105
vhd pc.vhd
-- pc.vhd
-- This module implements the 16-bit program Counter (PC). PC is loaded from
-- PCIn on the next clock when "PCControl" is asserted high. PC is cleared to
-- zero when "reset" is assert
www.eeworm.com/read/329969/12922829
bak uartrec.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity UartRec is
Port(
RESET :in std_logic;
RCLK :in std_logic;
www.eeworm.com/read/329969/12922878
bak ptxd.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PTXD is
Port(
TCLK,Reset :in std_logic;
SendEn,Clock:in std_logic;
INT :in std_logic;