ptxd.vhd.bak

PCM数据采集

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity PTXD is
Port(
    TCLK,Reset  :in  std_logic;
    SendEn,Clock:in  std_logic;
    INT			:in  std_logic; 
    tbr         :in  std_logic_vector(7 downto 0);
	dout        :out std_logic;
	tre         :buffer std_logic
	);
end entity;

architecture ATR_PTXD of PTXD is
   signal getadata :std_logic;
    
begin   --ATR

process(Clock,tre,RESET)
variable EnLast	:std_logic;
    begin   -------------------------------------------process
    if RESET='0' or  tre='0' then 
        getadata<='0';
        EnLast:='1';
    elsif Clock'event and Clock='1' then
    	if ( EnLast='0' and SendEn='1' ) or INT='0' then ---------INT='0' 说明来了中断
        	getadata<='1';
        end if;
        EnLast:=SendEn;
    end if;
end process;

process(TCLK,Reset)
        variable Tstate		:std_logic_vector(3 downto 0);
        variable tsr		:std_logic_vector(7 downto 0);
    begin   -----------------------------------------TXD process
    if Reset='0' then
        dout<='1';
        tre <='1';
        Tstate:=(others=>'0');
        tsr:=(others=>'0');
     elsif TCLK'event and TCLK='1' then
        if getadata='1' then 
            Tstate:="0110";
            tsr := tbr;--发送缓冲器tbr数据进入发送移位寄存器tsr
            tre <='0';	--发送移位寄存器空标志置'0'
            dout<='0';	--发送起始位
    	elsif Tstate >= "0110" and Tstate<="1101" then
	        dout <= tsr(0);
	        tsr :=INT & tsr(7 downto 1);--从低位到高位进行移位输出至串行输出端dout
	    elsif Tstate ="1110" then
	        dout<=tsr(0);
	    --  tre <= '1'; --发送完毕标志置'1' 
        elsif Tstate ="1111" then
	        dout <= '1'; --停止位输出
	        tre <= '1'; --发送完毕标志置'1' 
        end if;       
        if Tstate/="0000" then
            Tstate:=Tstate+1;
        end if;        
    end if;    
end process;
end ATR_PTXD;