uartrec.vhd.bak

来自「PCM数据采集」· BAK 代码 · 共 62 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity UartRec is
Port(
    RESET       :in  std_logic;
    RCLK		:in  std_logic;
    UartIn		:in  std_logic;
    DataRec    	:out std_logic_vector(8 downto 0);
	GetData		:out std_logic
    );
end entity;

architecture ATR_UartRec of UartRec is
signal 	Start	:std_logic;

begin   ---------------------------------------architecture begin

process(UartIn,GetData)--,RESET)--捕捉新数据到来
	begin
	if GetData='0' then
	    Start<='0';  --正在接收数据
	elsif UartIn'event and UartIn='0' then     --新数据来了
		Start<='1';
	end if;
end process;

process(RCLK,RESET)
variable Rstate	:std_logic_vector(5 downto 0);
variable rsr	:std_logic_vector(8 downto 0);
	begin
	if RESET='0' then
	    GetData<='1';
	    Rstate:="000000";
	    rsr:="000000000";
	    DataRec<="000000000";
	elsif RCLK'event and RCLK='1' then --上升沿来了开始接收
-------------------------------------------------------------------	
        if Start='1' then 
		    GetData<='0';
		    Rstate:="011000";--进入接收状态 24
		elsif Rstate(1 downto 0)="01" then  --25 29 33 37 41 45 49 53 57 61
			rsr(8 downto 0):=UartIn&rsr(8 downto 1);
		elsif Rstate="111110" then  --62
            DataRec<=rsr;
        --  GetData<='1';--有时提前发出会节约时间，
        --可是DataRec与GetData同时有效，不能保证GetData上升沿时正确获取DataRec。
        elsif Rstate="111111" then  --63 
          GetData<='1';--完成接收一帧数据    					
        end if;
-----------------------------------------------------------------        
		if Rstate/="000000" then
		    Rstate:=Rstate+1; --其余非0
		end if;
-----------------------------------------------------------------		
	end if;
end process;
end ATR_UartRec;