reg.vhd

来自「关于C++编程方向的一些经验」· VHDL 代码 · 共 46 行

-- reg.vhd

-- This module implements a 16-bit general purpose register. The contents of
-- register is loaded on the rising edge of "clk". It is cleared to zero when
-- "reset" is asserted low. The output of the register is its contents.

-- Inputs: 
--    DataIn    - 16-bit register input
--    reset     - 1-bit reset signal which clears the contents of register to zero when it is asserted low
--    clk       - 1-bit clock signal

-- Outputs: 
--    DataOut   - 16-bit register output

-- Author:    Easyright
-- E-mail:    [e-mail]
-- Date:      17-08-2003
-- Copyright: http://www.EasyRight.net

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity reg is
  port (
    DataIn:   in std_logic_vector(15 downto 0);
    reset:    in std_logic;
    clk:      in std_logic;
    DataOut:  out std_logic_vector(15 downto 0)
  );
end reg;

architecture arc_reg of reg is
begin
  process(clk, reset)
  begin
    if (reset = '0') then
      DataOut <= "0000000000000000";
    elsif rising_edge(clk) then
      DataOut <= DataIn;
    end if;
  end process;
end arc_reg;