代码搜索：std

找到约 10,000 项符合「std」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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vhd qregister.vhd

library IEEE; use IEEE.std_logic_1164.all; entity QRegister is port( op: in std_logic_vector(1 downto 0); clk: in std_logic; sr: in std_logic; din: in std_logic_vector(31 downto 0)
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bak qregister.vhd.bak

library IEEE; use IEEE.std_logic_1164.all; entity QRegister is port( op: in std_logic_vector(1 downto 0); clk: in std_logic; sr: in std_logic; din: in std_logic_vector(31 downto 0)
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bak aregister.vhd.bak

library IEEE; use IEEE.std_logic_1164.all; entity ARegister is port( op: in std_logic_vector(1 downto 0); clk: in std_logic; din: in std_logic_vector(31 downto 0); dout: out std_lo
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bak fifobuffer.vhd.bak

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY FIFOBuffer IS PORT( wclk : IN std_logic; rstb : IN std_logic; ISOP : IN std_logic; IE
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vhd fifobuffer.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY FIFOBuffer IS PORT( wclk : IN std_logic; rstb : IN std_logic; ISOP : IN std_logic; IE
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vhd e10281_obf.vhd

--------------------------------------------------------------------------- -- This VHDL file is generated by EASE/VHDL from TRANSLOGIC BV, -- the 'Entity Architecture Schematics Editor for VHDL' tool
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txt vhdl.txt

[VHDL]并口通讯代码（调试通过） --该代码目前能实现单个字节的收发 library ieee; use ieee.std_logic_1164.all; USE IEEE.Std_Logic_Unsigned.ALL; USE IEEE.Std_Logic_Arith.ALL; ENTITY MCU IS PORT ( nDataStrobe : IN Std_
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vhd counter60.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter60 is Port ( clk : in std_logic; reset : in std_logic;
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vhd counter100.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter100 is Port ( clk : in std_logic; reset : in std_logic;
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vhd counter24.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter24 is Port ( clk : in std_logic; reset : in std_logic;
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