counter100.vhd

来自「24,60,100进制的计数器」· VHDL 代码 · 共 47 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter100 is
    Port ( clk : in std_logic;
           reset : in std_logic;
          co : out std_logic;
          dl : buffer std_logic_vector(3 downto 0);
          dh : buffer std_logic_vector(3 downto 0) );
end counter100;
architecture Behavioral of counter100 is
signal count : std_logic_vector(7 downto 0);
begin
    dh <= count(7 downto 4);
    dl <= count(3 downto 0);

	process(clk,reset)
	begin
	   if reset= '0' then
		  count <= "00000000";
		        elsif rising_edge(clk) then	   
		   if count(3 downto 0)="1001" then
			 count(3 downto 0)<="0000";
			count(7 downto 4)<=count(7 downto 4) +1;
         else
			count(3 downto 0)<=count(3 downto 0)+1;
         end if;
         
           if (count(7 downto 4)="1001"and count(3 downto 0)="1001" )then
		   count<="00000000";
          end if;
        end if;
            end process;
   
   
   PROCESS(dh,dl,reset)
  BEGIN
   IF(reset='1' AND dl="1001" AND dh="1001") THEN
     co<='1';
   ELSE
     co<='0';
   END IF;
END PROCESS;

end Behavioral;