fifobuffer.vhd.bak

32bits FIFO with synchronizer. pass the synthesis using Synopsys tools

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY FIFOBuffer IS
    PORT(
        wclk   :   IN   std_logic;
        rstb   :   IN   std_logic;
        
        ISOP   :   IN   std_logic;
        IEOP   :   IN   std_logic;
        IVALID :   IN   std_logic;
        IREADY :   IN   std_logic;
        IDATA  :   IN   std_logic_vector(7 DOWNTO 0);

        rclk   :   IN   std_logic;
        
        OSOP   :   IN   std_logic;
        OEOP   :   IN   std_logic;
        OVALID :   IN   std_logic;
        ODATA  :   IN   std_logic_vector(7 DOWNTO 0)
        );
END FIFOBuffer;

ARCHITECTURE behav OF FIFOBuffer IS