代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/175784/9531207
vhd omet.vhd
--omet.vhd
--v0.1
--measure dff
library ieee;
use ieee.std_logic_1164.all;
entity omet is
port(
clk: in std_logic;
reset: in std_logic;
imet_0: in std_logic_vector(5 downto 0);
www.eeworm.com/read/371886/9532085
vhd txunit.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/371886/9532089
vhd miniuart.vhd
--===========================================================================--
--
-- S Y N T H E Z I A B L E miniUART C O R E
--
-- www.OpenCores.Org - January 2000
-- This core adheres
www.eeworm.com/read/175755/9534674
cmp nco.cmp
-- Generated by NCO 2.2.2 [Altera, IP Toolbench v1.2.7 build38]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- *******
www.eeworm.com/read/175563/9541206
vhd produce.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity produce is
port(
clk:in std_logic; --时钟
set:in std_logic; --预制
reset:in std_logic; --复位
www.eeworm.com/read/175563/9541304
vhd pro.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pro is
port(
clk:in std_logic; --时钟
set:in std_logic; --预置
reset:in std_logic; --复位
www.eeworm.com/read/371625/9544952
vhd uart_5kvg_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
www.eeworm.com/read/371625/9544953
vhd uart_top.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
www.eeworm.com/read/175328/9552050
vhd vga_main.vhd
---------------------------------------------------------------------
-- vga_main.vhd Demo VGA configuration module.
---------------------------------------------------------------------
-- Autho
www.eeworm.com/read/174989/9565683
vhd aregister.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity ARegister is
port( op: in std_logic_vector(1 downto 0);
clk: in std_logic;
din: in std_logic_vector(31 downto 0);
dout: out std_lo