aregister.vhd

来自「the booth algorithm to implement the 32b」· VHDL 代码 · 共 29 行

library IEEE;
use IEEE.std_logic_1164.all;

entity ARegister is 
port( op: in std_logic_vector(1 downto 0);
      clk: in std_logic;
      din: in std_logic_vector(31 downto 0);
      dout: out std_logic_vector(31 downto 0)
      );
end ARegister;

architecture behav of ARegister is
signal data: std_logic_vector(31 downto 0);
begin
reg: process(clk)
begin
    if (clk'event and clk = '1') then
        if (op = "01") then
            --data <= din>>1;
            data <= (31 downto 31 => '0') & din(31 downto 1);
        elsif (op = "10" or op = "11") then
            data <= (others=>'0');
        end if;
        
        dout <= data;
    end if;
end process;
end behav;