omet.vhd

来自「提供了一个硬判决的viterbi译码器（2」· VHDL 代码 · 共 43 行

--omet.vhd
--v0.1
--measure dff

library ieee;
use ieee.std_logic_1164.all;

entity omet is
	port(
		clk: in std_logic;
		reset: in std_logic;
		imet_0: in std_logic_vector(5 downto 0);
		imet_1: in std_logic_vector(5 downto 0);
		imet_2: in std_logic_vector(5 downto 0);
		imet_3: in std_logic_vector(5 downto 0);
		omet_0: out std_logic_vector(5 downto 0);
		omet_1: out std_logic_vector(5 downto 0);
		omet_2: out std_logic_vector(5 downto 0);
		omet_3: out std_logic_vector(5 downto 0)
		);
end omet;

architecture a of omet is
begin
	process(clk,reset,imet_0,imet_1,imet_2,imet_3)
	begin
		if rising_edge(clk) then
			if reset='1' then
			omet_0<="000000";
			omet_1<="000000";
			omet_2<="100000";
			omet_3<="100000";
			else
			omet_0<=imet_0;
			omet_1<=imet_1;
			omet_2<=imet_2;
			omet_3<=imet_3;
			end if;
		end if;
	end process;
end a;