代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/287512/8684596
vhd ahb_package.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package ahb_package is
-----------------------------------------------------------------------------
-- Generic contants
---
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vhd mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
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vhd mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
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vhd uart.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:37:27 03/13/09
-- Design Name:
-- Module Name: uart - B
www.eeworm.com/read/286093/8788741
vhf top.vhf
-- VHDL model created from top.sch - Wed Jun 20 18:35:50 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcompo
www.eeworm.com/read/429615/8798819
vhd lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd is
Port ( clk : in std_logic; --4MHZ FROM D12
Reset
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vhd timer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TIMER IS
PORT( iclk : IN STD_LOGIC; --input clock
iRst : IN STD_LOGIC;
iNF: IN STD_LOGIC;
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bak timer.vhd.bak
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TIMER IS
PORT( iclk : IN STD_LOGIC; --input clock
iRst : IN STD_LOGIC;
iNF: IN STD_LOGIC;
iSMin: IN STD_
www.eeworm.com/read/285898/8802867
vhd ddfs.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY ddfs IS
PORT (clk,P12 : IN Std_logic;
P13: INOUT Std_logic;
wr: OUT Std_logic;
da
www.eeworm.com/read/428962/8826704
vhd counter.vhd
library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;
entity counter is
generic(n: NATURAL := 16);
port( clock: in std_logic;
reset: in std_logic;
se