counter.vhd

来自「可预置16位计数器可预置16位计数器可预置16位计数器」· VHDL 代码 · 共 31 行

library IEEE;
use IEEE.std_logic_1164.all, IEEE.numeric_std.all;

entity counter is
    generic(n: NATURAL := 16);
    port( clock: in std_logic;
            reset: in std_logic;
            set: in std_logic;
            lock: in std_logic;
            pin: in std_logic_vector(n-1 downto 0);   
            count: out std_logic_vector(n-1 downto 0));
end entity counter;

architecture rtl of counter is
   begin
p0: process(clock, reset, set, lock, pin) is
     variable cnt : unsigned(n-1 downto 0);
   begin
       if reset = '1' then
         cnt := (others => '0');
       elsif set = '1' then
         cnt := unsigned(pin);
       elsif lock = '1' then
         cnt := cnt;
       elsif rising_edge(clock) then
         cnt := cnt + 1;
       end if;
       count <= std_logic_vector(cnt);
end process p0;
end architecture rtl;