uart.vhd

一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    17:37:27 03/13/09
-- Design Name:    
-- Module Name:    uart - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
--===============================================================================
--功能：完成通用异步收发器（UART）的设计
--说明：顶层程序由三个模块（baud、reciever、transfer）构成
--最后修改时间：2003年7月10日
--===============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity top is
    Port (clk32mhz	  :in std_logic;		  --时钟信号
	       reset		  :in std_logic;		  --复位信号
	       rxd			  :in std_logic;				--接收
	       xmit_cmd_p_in:in std_logic;        --总的输入输出信号的定义
          txdbuf_in    :in std_logic_vector(7 downto 0);
          rec_ready	  :out std_logic;
			 txd_out		  :out std_logic;
			 txd_done_out :out std_logic;

			 clkout       :out std_logic;



          rec_buf      :out std_logic_vector(7 downto 0));               
end top;
 
architecture behavioral of top is
component reciever
    Port (bclkr	     :in std_logic;
	       resetr       :in std_logic;
			 rxdr         :in std_logic;
          r_ready      :out std_logic;
          rbuf         :out std_logic_vector(7 downto 0));
end component;
component transfer
    Port (bclkt		  :in std_logic;
	       resett		  :in std_logic;
			 xmit_cmd_p   :in std_logic;
          txdbuf       :in std_logic_vector(7 downto 0);
          txd          :out std_logic;
          txd_done     :out std_logic);
end component;
component baud
    Port (clk			  :in std_logic;
	       resetb       :in std_logic;
          bclk         :out std_logic);
end component;

signal b:std_logic;

begin
u1:baud     port map(clk       =>clk32mhz,
                     resetb    =>reset,
					      bclk      =>b);             --顶层映射
u2:reciever port map(bclkr     =>b,
                     resetr    =>reset,
							rxdr      =>rxd,
							r_ready   =>rec_ready,
                     rbuf      =>rec_buf);
u3:transfer port map(bclkt     =>b,
                     resett    =>reset,
							xmit_cmd_p=>xmit_cmd_p_in,
                     txdbuf    =>txdbuf_in,
							txd       =>txd_out,
							txd_done  =>txd_done_out);




clkout<=b;
 
end behavioral;