ddfs.vhd

一个直接数字频率合成的查表程序,VHDL语言,使用7128调试通过

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
 
ENTITY ddfs IS 
   PORT (clk,P12 : IN Std_logic; 
         P13: INOUT Std_logic;
		 wr: OUT Std_logic;
         datin : IN Std_logic_vector(7 DOWNTO 0);
         addr: OUT Std_logic_vector(10 DOWNTO 0));
END ddfs;

ARCHITECTURE LOAD_COUNT OF ddfs IS
 
   SIGNAL count : Std_logic_vector(30 DOWNTO 0);
   SIGNAL rule : Std_logic_vector(23 DOWNTO 0);
   SIGNAL 	ce0,ce1:Std_logic;
   TYPE STATE_TYPE IS (s0, s1,s2,s3,s4);
   SIGNAL state	: STATE_TYPE;
BEGIN
   PROCESS(clk)
   BEGIN
ce1<=datin(7);
ce0<=datin(6);
    IF P12='0' THEN
                    addr(6 downto 0)<= count(30 DOWNTO 24);
					addr(10 downto 7)<="0000";
                    state <= s0;
	ELSIF (clk'EVENT AND clk = '1') THEN
      CASE state IS
                WHEN s0=>
                    state<=s1;
				WHEN s1=>
                    addr<="00001010001";
                    IF ((CE0 OR CE1)='1') THEN
                      state<=s1;
                    else       
                    rule(5 DOWNTO 0)<=datin(5 DOWNTO 0);
					state <= s2;
                    end if;
				WHEN s2=>
                    addr<="00001010010";
                    IF ((CE0 OR (NOT CE1))='1') THEN
                      state<=s2;
                    else       
                    rule(11 DOWNTO 6)<=datin(5 DOWNTO 0);
					state <= s3;
                    end if;
                WHEN s3=>
                    addr<="00001010011";
                    IF (((NOT CE0) OR CE1)='1') THEN
                      state<=s3;
                    else       
                    rule(17 DOWNTO 12)<=datin(5 DOWNTO 0);
					state <= s4;
                    end if;
                WHEN S4=>
                    addr<="00001010100";
                    IF (((NOT CE0) OR (NOT CE1))='1') THEN
                      state<=s4;
                    else       
                    rule(23 DOWNTO 18)<=datin(5 DOWNTO 0);
					state <= s1;
                    end if;
        END CASE;
      END IF;  
    END PROCESS;
  
   PROCESS(clk)
   BEGIN
      IF (clk'EVENT AND clk = '1') THEN
         IF P12='1' THEN
           count<="0000000000000000000000000000000";
         else
           count <= count + rule;
         END IF;
      END IF; 
   END PROCESS;
   p13<='0' WHEN count>"111111111111111111000000000000";
   wr<='1' WHEN  count(22 downto 22)="0" else '0';
END LOAD_COUNT;