top.vhf

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-- VHDL model created from top.sch - Wed Jun 20 18:35:50 2007


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity top is
   port ( clk      : in    std_logic; 
          en       : in    std_logic; 
          qd       : in    std_logic_vector (7 downto 0); 
          baojing  : out   std_logic; 
          time1    : out   std_logic_vector (6 downto 0); 
          time2    : out   std_logic_vector (6 downto 0); 
          xuanshou : out   std_logic_vector (6 downto 0));
end top;

architecture BEHAVIORAL of top is
   signal XLXN_20  : std_logic_vector (3 downto 0);
   signal XLXN_21  : std_logic_vector (3 downto 0);
   signal XLXN_27  : std_logic;
   signal XLXN_29  : std_logic_vector (3 downto 0);
   signal XLXN_38  : std_logic;
   signal XLXN_40  : std_logic;
   component ymq
      port ( int  : in    std_logic_vector (3 downto 0); 
             out7 : out   std_logic_vector (6 downto 0));
   end component;
   
   component bjq
      port ( b1     : in    std_logic; 
             b2     : in    std_logic; 
             b3     : in    std_logic; 
             clkin1 : in    std_logic; 
             bout   : out   std_logic);
   end component;
   
   component dsq
      port ( en1    : in    std_logic; 
             hold   : in    std_logic; 
             clkin1 : in    std_logic; 
             q2     : out   std_logic; 
             data1  : out   std_logic_vector (3 downto 0); 
             data2  : out   std_logic_vector (3 downto 0));
   end component;
   
   component fpq
      port ( clkin  : in    std_logic; 
             clkout : out   std_logic);
   end component;
   
   component qdq
      port ( en    : in    std_logic; 
             q1    : out   std_logic; 
             clk   : in    std_logic; 
             q2    : in    std_logic; 
             qiang : in    std_logic_vector (7 downto 0); 
             qz    : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_5 : ymq
      port map (int(3 downto 0)=>XLXN_29(3 downto 0), out7(6 downto
            0)=>xuanshou(6 downto 0));
   
   XLXI_10 : bjq
      port map (b1=>en, b2=>XLXN_38, b3=>XLXN_40, clkin1=>XLXN_27,
            bout=>baojing);
   
   XLXI_11 : dsq
      port map (clkin1=>XLXN_27, en1=>en, hold=>XLXN_38, data1(3 downto
            0)=>XLXN_20(3 downto 0), data2(3 downto 0)=>XLXN_21(3 downto 0),
            q2=>XLXN_40);
   
   XLXI_12 : ymq
      port map (int(3 downto 0)=>XLXN_20(3 downto 0), out7(6 downto 0)=>time1(6
            downto 0));
   
   XLXI_13 : ymq
      port map (int(3 downto 0)=>XLXN_21(3 downto 0), out7(6 downto 0)=>time2(6
            downto 0));
   
   XLXI_14 : fpq
      port map (clkin=>clk, clkout=>XLXN_27);
   
   XLXI_16 : qdq
      port map (clk=>clk, en=>en, qiang(7 downto 0)=>qd(7 downto 0),
            q2=>XLXN_40, qz(3 downto 0)=>XLXN_29(3 downto 0), q1=>XLXN_38);
   
end BEHAVIORAL;