代码搜索：modelSim

找到约 1,834 项符合「modelSim」的源代码

代码结果 1,834
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/255557/12074160

bat run.bat

REM Ensure that you have the QuartusII 3.1SP2 precompiled libraries installed REM Change this next line to point to your ModelSim AE installation directory set MODELSIM_DIR=c:\modelsim\ae5.7c set P
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www.eeworm.com/read/152706/12091641

_info

m255 13 cModel Technology dG:\taoyuhui\modelsim_work\examples_from_books\11.2 vdrink_machine I?2TWzd5iiI?B@`eO[EAE83 VN@6XdaLa8Y4K2ZLZ`SZ?93 w1141305376 FG:/taoyuhui/modelsim_work/examples_from_books/
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www.eeworm.com/read/127647/14345929

transcript

# Reading e:/modelsim/tcl/vsim/pref.tcl # do pn_encode_pn_code_test_v_tf.fdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vlog 5.7c Compiler 2003.03
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www.eeworm.com/read/214883/15085092

ptf pn_gen_ver_211.ptf

[iq_pn_gen] Place & Route=false Implement Design=true Map=true Generate Post-Map Static Timing=true [pn_gen_srl_test.tf] ModelSim Simulator=true
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www.eeworm.com/read/206514/15294018

ptf pn_gen_ver_211.ptf

[iq_pn_gen] Place & Route=false Implement Design=true Map=true Generate Post-Map Static Timing=true [pn_gen_srl_test.tf] ModelSim Simulator=true
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www.eeworm.com/read/154076/5643176

gfl alu_vlog.gfl

# Synplify flow : synCreateProject __projnav/__synProj.rsp alu.prj __projnav/alu.ise_created alu_compile.tcl alu_map.tcl # files created during Synthesis stdout.log stderr.log alu.srs alu.sr
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www.eeworm.com/read/375321/9364167

rpt top_nativelink_simulation.rpt

Info: Start Nativelink Simulation process Info: NativeLink has detected Verilog design -- Verilog simulation models will be used ========= EDA Simulation Settings ===================== Sim Mode
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www.eeworm.com/read/424904/10401921

sft sram_test.sft

set tool_name "ModelSim (Verilog)" set corner_file_list { {{"Slow Model"} {sram_test.vo sram_test_v.sdo}} }
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www.eeworm.com/read/130423/14194825

_info

m255 cModel Technology dD:\Modeltech_5.7d\YYH_ModelSim_Examples\Viterbi_ASIC_Book vconv_encode IJlHBUzOg3PV6IN:mdF5jm2 V5Y0HR:gE`cRUi?C=OQ:g82 dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen2 w1057200
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www.eeworm.com/read/130423/14194887

_info

m255 cModel Technology dD:\Modeltech_5.7d\YYH_ModelSim_Examples\Viterbi_ASIC_Book vconvl3_en I8lk8[Q9b
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