_info

发一个基于ModelSim仿真的Verilog源代码包

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cModel Technology
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\Viterbi_ASIC_Book
vconvl3_en
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VOhZOf8@eK1[DXMcZ:=fCf0
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen3
w1054869624
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen3/convl3_en.v
L0 13
OE;L;5.7d;17
r1
31
o-work work
vconvlen3_test
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dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen3
w1054870332
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen3/convlen3_test.v
L0 18
OE;L;5.7d;17
r1
31
o-work work
vdff
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dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen3
w1049250368
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen3/dff.v
L0 6
OE;L;5.7d;17
r1
31
o-work work