_primary.vhd

来自「发一个基于ModelSim仿真的Verilog源代码包」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity conv_encode is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        x_unsync        : in     vl_logic;
        z               : out    vl_logic
    );
end conv_encode;