convl_en.v

来自「发一个基于ModelSim仿真的Verilog源代码包」· Verilog 代码 · 共 31 行

/******************************************************/
/* module convl_en                              */
/******************************************************/

/* This is the encoder. 
X1N (msb)  form the 1-bit input message, XN. 
Y3N (msb), Y2N,Y1N, and Y0N form the 3-bit encoded signal, YN (for a total constellation of 8
PSK signals that will be transmitted). The encoder uses a state
machine with four states to generate the 4-bit output, YN, from the
1-bit input, XN.Polynomial:133,171,145,133   K=7
*/
module convl_en(X1N,Y3N,Y2N,Y1N,Y0N,clk,res);
input X1N,clk,res; 
output Y3N,Y2N,Y1N,Y0N;
wire X1N_0,X1N_1,X1N_2,X1N_3,X1N_4,X1N_5,X1N_6,Y2N,Y1N,Y0N;

dff dff_0(X1N,X1N_0,clk,res); //X1N is direct input data,x1N_0 is sampled valid data from X1N at clock edage 
dff dff_1(X1N_0,X1N_1,clk,res); 
dff dff_2(X1N_1,X1N_2,clk,res);
dff dff_3(X1N_2,X1N_3,clk,res); 
dff dff_4(X1N_3,X1N_4,clk,res);
dff dff_5(X1N_4,X1N_5,clk,res); 
dff dff_6(X1N_5,X1N_6,clk,res);

assign Y3N=X1N_0 ^ X1N_2 ^ X1N_3 ^ X1N_5 ^ X1N_6; //Y3N=Y0N
assign Y2N=X1N_0 ^ X1N_1 ^ X1N_2 ^ X1N_3 ^ X1N_6; 
assign Y1N=X1N_0 ^ X1N_1 ^ X1N_4 ^ X1N_6; 
assign Y0N=X1N_0 ^ X1N_2 ^ X1N_3 ^ X1N_5 ^ X1N_6; 
endmodule