_primary.vhd

来自「发一个基于ModelSim仿真的Verilog源代码包」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity ser2par is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        serialdata      : in     vl_logic;
        pardata         : out    vl_logic_vector(1 downto 0)
    );
end ser2par;