pn_gen_ver_211.ptf

FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载

[iq_pn_gen]
Place & Route=false
Implement Design=true
Map=true
Generate Post-Map Static Timing=true
[pn_gen_srl_test.tf]
ModelSim Simulator=true