top_nativelink_simulation.rpt

sdram 控制器的verilog 实现

Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used

========= EDA Simulation Settings =====================

Sim Mode              :  RTL
Family                :  cyclone
Quartus root          :  d:/program files/quartus7_2/quartus/bin/
Quartus sim root      :  d:/program files/quartus7_2/quartus/eda/sim_lib
Simulation Tool       :  modelsim-altera
Simulation Language   :  verilog
Simulation Mode       :  GUI
Sim Output File       :  top.vo
Sim SDF file          :  top__verilog.sdo
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script d:/program files/quartus7_2/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File top_run_msim_rtl_verilog.do already exists - backing up current file as top_run_msim_rtl_verilog.do.bak11
Probing transcript
ModelSim-Altera Info: # Reading C:/altera/72/modelsim_ae/tcl/vsim/pref.tcl 
ModelSim-Altera Info: # do top_run_msim_rtl_verilog.do 
ModelSim-Altera Info: # if {[file exists rtl_work]} {
ModelSim-Altera Info: # 	vdel -lib rtl_work -all
ModelSim-Altera Info: # }
ModelSim-Altera Info: # vlib rtl_work
ModelSim-Altera Info: # vmap work rtl_work
ModelSim-Altera Info: # Modifying C:\altera\72\modelsim_ae\win32aloem/../modelsim.ini
ModelSim-Altera Info: # 
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all {E:/pratice/verilog/sdram_controller/sdram_all/top.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module top
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	top
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_user {E:/pratice/verilog/sdram_controller/sdram_all/source_user/ram512.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module ram512
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	ram512
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_user {E:/pratice/verilog/sdram_controller/sdram_all/source_user/rom256.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module rom256
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	rom256
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_user {E:/pratice/verilog/sdram_controller/sdram_all/source_user/user_interface.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module user_interface
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	user_interface
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/refresh.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module refresh
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	refresh
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdr_par.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdram_top.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module sdram_top
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	sdram_top
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/init_fsm.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module init_fsm
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	init_fsm
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/main_fsm.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module main_fsm
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	main_fsm
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/source_sdram {E:/pratice/verilog/sdram_controller/sdram_all/source_sdram/sdr_sig.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module sdr_sig
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	sdr_sig
ModelSim-Altera Info: # 
ModelSim-Altera Info: # vlog -vlog01compat -work work +incdir+E:/pratice/verilog/sdram_controller/sdram_all/testbench {E:/pratice/verilog/sdram_controller/sdram_all/testbench/testbench.v}
ModelSim-Altera Info: # Model Technology ModelSim ALTERA vlog 6.1g Compiler 2006.08 Aug 12 2006
ModelSim-Altera Info: # -- Compiling module tb
ModelSim-Altera Info: # 
ModelSim-Altera Info: # Top level modules:
ModelSim-Altera Info: # 	tb
ModelSim-Altera Info: # 
ModelSim-Altera Info: # vsim -t 1ps -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cyclone_ver -L rtl_work -L work tb
ModelSim-Altera Info: # vsim -L lpm_ver -L altera_ver -L altera_mf_ver -L sgate_ver -L cyclone_ver -L rtl_work -L work -t 1ps tb 
ModelSim-Altera Info: # //  ModelSim ALTERA 6.1g Aug 12 2006 
ModelSim-Altera Info: # //
ModelSim-Altera Info: # //  Copyright 2006 Mentor Graphics Corporation
ModelSim-Altera Info: # //              All Rights Reserved.
ModelSim-Altera Info: # //
ModelSim-Altera Info: # //  THIS WORK CONTAINS TRADE SECRET AND 
ModelSim-Altera Info: # //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
ModelSim-Altera Info: # //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
ModelSim-Altera Info: # //  AND IS SUBJECT TO LICENSE TERMS.
ModelSim-Altera Info: # //
ModelSim-Altera Info: # Loading rtl_work.tb
ModelSim-Altera Info: # Loading rtl_work.top
ModelSim-Altera Warning: # ** Warning: (vsim-3009) [TSCALE] - Module 'top' does not have a `timescale directive in effect, but previous modules do.
ModelSim-Altera Info: #         Region: /tb/top_inst
ModelSim-Altera Info: # Loading rtl_work.sdram_top
ModelSim-Altera Info: # Loading rtl_work.main_fsm
ModelSim-Altera Info: # Loading rtl_work.init_fsm
ModelSim-Altera Info: # Loading rtl_work.refresh
ModelSim-Altera Info: # Loading rtl_work.sdr_sig
ModelSim-Altera Info: # Loading rtl_work.user_interface
ModelSim-Altera Info: # Loading rtl_work.rom256
ModelSim-Altera Info: # Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.altsyncram
ModelSim-Altera Info: # Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_DEVICE_FAMILIES
ModelSim-Altera Info: # Loading C:\altera\72\modelsim_ae\win32aloem/../altera/verilog/altera_mf.ALTERA_MF_MEMORY_INITIALIZATION
ModelSim-Altera Info: # Loading rtl_work.ram512
ModelSim-Altera Info: # 
ModelSim-Altera Info: # do E:/pratice/verilog/sdram_controller/sdram_all/testbench/singal.do
ModelSim-Altera Info: # virtual type {
ModelSim-Altera Info: # {4'b0000 c_IDLE}
ModelSim-Altera Info: # {4'b0001 c_AR}
ModelSim-Altera Info: # {4'b0010 c_tRFC}
ModelSim-Altera Info: # {4'b0011 c_RW_AR}
ModelSim-Altera Info: # {4'b0100 c_RW_tRFC}
ModelSim-Altera Info: # {4'b0101 c_ACTIVE}
ModelSim-Altera Info: # {4'b0110 c_tRCD}
ModelSim-Altera Info: # {4'b0111 c_READ}
ModelSim-Altera Info: # {4'b1000 c_RD_DATA}
ModelSim-Altera Info: # {4'b1001 c_R_PRE}
ModelSim-Altera Info: # {4'b1010 c_R_tRP}
ModelSim-Altera Info: # {4'b1011 c_WRITE}
ModelSim-Altera Info: # {4'b1100 c_WR_DATA}
ModelSim-Altera Info: # {4'b1101 c_W_PRE}
ModelSim-Altera Info: # {4'b1110 c_W_tRP}
ModelSim-Altera Info: # } c_FSM_TYPE;
ModelSim-Altera Info: # 
ModelSim-Altera Info: # virtual type {
ModelSim-Altera Info: # {3'b000 i_NOP}
ModelSim-Altera Info: # {3'b001 i_PRE}
ModelSim-Altera Info: # {3'b010 i_tRP}
ModelSim-Altera Info: # {3'b011 i_AR}
ModelSim-Altera Info: # {3'b100 i_tRFC}
ModelSim-Altera Info: # {3'b101 i_MRS}
ModelSim-Altera Info: # {3'b110 i_tMRD}