_info

发一个基于ModelSim仿真的Verilog源代码包

m255
cModel Technology
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\Viterbi_ASIC_Book
vconv_encode
IJlHBUzOg3PV6IN:mdF5jm2
V5Y0HR:gE`cRUi?C=OQ:g82
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen2
w1057200278
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen2/ConvEncdJA.v
L0 24
OE;L;5.7d;17
r1
31
o-work work
vConvEncdTestBnch
IHH`E6`THRBjVb4]SbAnmz3
VGN[:YP3FbBXST]K3MhZzF1
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen2
w1053765544
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen2/ConvEncdTestBnch.v
L0 3
OE;L;5.7d;17
r1
31
o-work work
n@conv@encd@test@bnch
vser2par
I8J[DTO9?Dbf0SKDHSocdY0
VM8d=dLIeZ9PMF:^o;4:h11
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen2
w1057200278
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen2/ConvEncdJA.v
L0 58
OE;L;5.7d;17
r1
31
o-work work
vtop_encode
Ih1z:l^A24PB1XSSaDCRLM2
VN[L[;JH`5K4CW]P]Na`8f2
dD:\Modeltech_5.7d\YYH_ModelSim_Examples\covlen2
w1057200278
FD:/Modeltech_5.7d/YYH_ModelSim_Examples/covlen2/ConvEncdJA.v
L0 7
OE;L;5.7d;17
r1
31
o-work work