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cpp pgm14_07.cpp
//
// This file contains the C++ code from Program 14.7 of
// "Data Structures and Algorithms
// with Object-Oriented Design Patterns in C++"
// by Bruno R. Preiss.
//
// Copyright (c) 1998
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c tasksegleddisp.c
/********************************************************************
//
// Author: CaiXinBo \\\\\\\ //
//
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h xram.h
extern BYTE xdata IICCTR ; // _at_ 0xf00;
extern BYTE xdata IICSTUS ; // _at_ 0xf01;
extern BYTE xdata INTFLG ; // _at_ 0xf03;
extern BYTE xdata INTEN ; // _at_ 0xf04;
extern BYTE
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m fig2_22.m
%
% This file generates the graphs of the characteristic
% impedance for the microstrip line of two different
% metallization thicknesses
%
% Copyright (c) 1999 by P.Bretchko and R.Lud
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v adders_tp.v
module adders_tp;
reg [15:0] P1,P2;
wire [15:0] P3;
parameter DELY=100;
adders myadders(P1,P2,P3);
initial
begin P1=0;P2=0;
#DELY P1=16'b1010100101011100;P2=16'b0101101101010011;
#DELY P1=16'b0001
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v wallance_tp.v
module wallance_tp;
reg [9:0] part1,part2,part3,part4;
reg [7:0] temp;
wire [15:0] P;
parameter DELY=100;
wallance mywallance(part1,part2,part3,part4,temp,P);
initial
begin part1=0; part2=0; part3
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v multiple_tp.v
module multiple_tp;
reg [7:0] hin;
reg [8:0] x;
reg reset,clk2;
wire [15:0] P;
parameter DELY=100;
multiple multiple1(hin,clk2,x,reset,P);
always #(DELY/2) clk2=~clk2;
initial begin hin=0; x=0; reset=
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v bit_op.v
module bit_op();
reg [3:0] a, b, c;
initial begin
a=4'b0011; b=4'b1101; c=4'b1010;
$display (~a); //display 4'b1100 = 12
$display (a&b); //display 4'b0001 = 1
$display (a|c); /
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txt string.v.txt
//
// Demonstrate how to display strings for a particular signal.
// This allows you to see a text string for a bus, which at times, might
// help out in debugging. This is not intended for synthe
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m comp_wls.m
% Demonstration of Wiener filter,LMS filter,Steep-descent algorithm
clear;
clc;
N = 10000; %----- the length of the observation sequence
M = 2; %----- the filter length