multiple_tp.v

来自「Verilog 编写的fir滤波器」· Verilog 代码 · 共 24 行

module multiple_tp;
reg [7:0] hin;
reg [8:0] x;
reg reset,clk2;
wire [15:0] P;
parameter DELY=100;
multiple multiple1(hin,clk2,x,reset,P);
always #(DELY/2) clk2=~clk2;
initial begin hin=0; x=0; reset=1;clk2=0;
#DELY reset=0;
#DELY reset=1;
#DELY hin=0; x=0;
#DELY hin=76; x=-53;
#DELY hin=76; x=-54;
#DELY hin=15; x=36;
#DELY hin=1; x=36;
#DELY hin=15; x=0;
#DELY hin=8'b11111111; x=9'b100000000;
#DELY hin=8'b01111111; x=9'b100000000;
#DELY hin=8'b01111111; x=9'b011111111;
#(DELY*10) $finish;
end
initial $monitor($time,,,"hin=%d clk2=%d x=%d reset=%d P=%d",hin,clk2,x,reset,P);
endmodule