wallance_tp.v

Verilog 编写的fir滤波器

module wallance_tp;  
reg [9:0] part1,part2,part3,part4;  
reg [7:0] temp;
wire [15:0] P;
parameter DELY=100;
wallance mywallance(part1,part2,part3,part4,temp,P);
initial
begin part1=0; part2=0; part3=0; part4=0; temp=0;
#DELY part1=10'b1010101110; part2=10'b1010110000; part3=10'b1010111100; part4=10'b1011101110; temp=8'b00101001;
#DELY part1=10'b0101101110; part2=10'b1110010000; part3=10'b1010111100; part4=10'b0110111110; temp=8'b00100110;
#DELY part1=10'b0101110110; part2=10'b1100001010; part3=10'b1010011110; part4=10'b1011111010; temp=8'b01001010;
#DELY part1=10'b1111010100; part2=10'b1010000110; part3=10'b1010101110; part4=10'b1011110101; temp=8'b10010010;
#DELY part1=10'b1111111111; part2=10'b1111111111; part3=10'b1111111111; part4=10'b1111111111; temp=8'b10010101;
#(DELY*10) $finish;
end
initial $monitor($time,,,"part1=%d part2=%d part3=%d part4=%d temp=%d P=%d",part1,part2,part3,part4,temp,P);
endmodule