adders_tp.v

Verilog 编写的fir滤波器

module adders_tp;  
reg [15:0] P1,P2;  
wire [15:0] P3;
parameter DELY=100;
adders myadders(P1,P2,P3);
initial
begin P1=0;P2=0;
#DELY P1=16'b1010100101011100;P2=16'b0101101101010011;
#DELY P1=16'b0001011100101001;P2=16'b1001010110000101;
#DELY P1=16'b1000101011011100;P2=16'b0101011111001000;
#(DELY*10) $finish;
end
initial $monitor($time,,,"P1=%d P2=%d P3=%d ",P1,P2,P3);
endmodule