代码搜索:dataIn

找到约 2,888 项符合「dataIn」的源代码

代码结果 2,888
www.eeworm.com/read/165586/10056847

pas uapublic.pas

{******************************************************************************************} { } { Univ
www.eeworm.com/read/165425/10062693

v udualfifo.v

`timescale 1 ns / 100 ps module Udualfifo (waddr, datain, clk, wren, raddr, dataout); input [4:0] waddr; input [7:0] datain; input clk; input wren; input [4:0] raddr; ou
www.eeworm.com/read/165425/10062697

v udualfiforx.v

`timescale 1 ns / 100 ps module Udualfiforx (waddr, datain, clk, wren, raddr, dataout); input [4:0] waddr; input [7:0] datain; input clk; input wren; input [4:0] raddr;
www.eeworm.com/read/165425/10062712

v udualfiforx_tmpl.v

/* parameterized module instance */ /* Inputs */ /* .waddr ports : waddr[4:0] */ /* .datain ports : datain[7:0] */ /* .clk port : clk */ /* .wren
www.eeworm.com/read/165425/10062769

v udualfifo_tmpl.v

/* parameterized module instance */ /* Inputs */ /* .waddr ports : waddr[4:0] */ /* .datain ports : datain[7:0] */ /* .clk port : clk */ /* .wren
www.eeworm.com/read/360577/10086956

txt ezhihuan.txt

//这里的E置换是指扩展置换以及随后的相异或的结果 module ezhihuan(datain,keyin,b); input [32:1]datain; input [48:1]keyin; output [48:1]b; reg [48:1]b; reg [48:1] E; assign E[48:1] = {datain[32], datain[1]
www.eeworm.com/read/359177/10162413

m ch7example12prog1.m

% ch7example12prog1.m close all; clear; Ts=1e-3; % 码元时隙Ts=1ms ,相应地码速率为1000bps r=0.5; % 滚降系数 t=(-10e-3):1e-4:10e-3; % 时间从-10ms 到+10ms 共20 个时隙 [num,den] = rcosine(1e
www.eeworm.com/read/359174/10162642

v test3.v

`timescale 1ns / 1ps //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 17:11:30 01/11/2008 // Design Name: shuju
www.eeworm.com/read/359174/10162955

v shuju.v

module shuju(rst,sclk,sdata); input rst,sclk; output sdata; reg sdata; reg [4:0]count,zhuangtai; reg [15:0]datain; always@(negedge sclk) if(!rst) begin sdata
www.eeworm.com/read/359174/10163222

v data.v

module data(sclk,sdata); input sclk; output sdata; reg sdata; reg [4:0]e,state6; reg [15:0]datain; initial begin sdata