udualfifo.v

USBRTL电路的VHDL和Verilog代码

`timescale 1 ns / 100 ps
module Udualfifo (waddr, datain, clk, wren, raddr, dataout);
    input [4:0] waddr;
    input [7:0] datain;
    input clk;
    input wren;
    input [4:0] raddr;
    output [7:0] dataout;

    INV INV_1 (.A(waddr[4]), .Z(waddr4_inv));
    INV INV_0 (.A(raddr[4]), .Z(raddr4_inv));
    DCF16X2Z mem_0_0_7 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[6]), .DI1(datain[7]), .CK(clk), .WREN(wren), 
        .WPE(waddr4_inv), .TRI(raddr[4]), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[6]), .RDO1(dataout[7]));
    DCF16X2Z mem_0_1_6 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[4]), .DI1(datain[5]), .CK(clk), .WREN(wren), 
        .WPE(waddr4_inv), .TRI(raddr[4]), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[4]), .RDO1(dataout[5]));
    DCF16X2Z mem_0_2_5 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[2]), .DI1(datain[3]), .CK(clk), .WREN(wren), 
        .WPE(waddr4_inv), .TRI(raddr[4]), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[2]), .RDO1(dataout[3]));
    DCF16X2Z mem_0_3_4 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[0]), .DI1(datain[1]), .CK(clk), .WREN(wren), 
        .WPE(waddr4_inv), .TRI(raddr[4]), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[0]), .RDO1(dataout[1]));
    DCF16X2Z mem_1_0_3 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[6]), .DI1(datain[7]), .CK(clk), .WREN(wren), 
        .WPE(waddr[4]), .TRI(raddr4_inv), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[6]), .RDO1(dataout[7]));
    DCF16X2Z mem_1_1_2 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[4]), .DI1(datain[5]), .CK(clk), .WREN(wren), 
        .WPE(waddr[4]), .TRI(raddr4_inv), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[4]), .RDO1(dataout[5]));
    DCF16X2Z mem_1_2_1 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[2]), .DI1(datain[3]), .CK(clk), .WREN(wren), 
        .WPE(waddr[4]), .TRI(raddr4_inv), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[2]), .RDO1(dataout[3]));
    DCF16X2Z mem_1_3_0 (.AD0(waddr[0]), .AD1(waddr[1]), .AD2(waddr[2]), 
        .AD3(waddr[3]), .DI0(datain[0]), .DI1(datain[1]), .CK(clk), .WREN(wren), 
        .WPE(waddr[4]), .TRI(raddr4_inv), .RAD0(raddr[0]), .RAD1(raddr[1]), 
        .RAD2(raddr[2]), .RAD3(raddr[3]), .RDO0(dataout[0]), .RDO1(dataout[1]));
endmodule