📄 shuju.v
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module shuju(rst,sclk,sdata);
input rst,sclk;
output sdata;
reg sdata;
reg [4:0]count,zhuangtai;
reg [15:0]datain;
always@(negedge sclk)
if(!rst)
begin
sdata<=0;
count<=0;
datain<=16'b0000000100000000; //configuration
zhuangtai<=0;
end
else
case(zhuangtai)
0:if(count==16)
begin
datain<=16'b0001000110010000; //PGA gain:400(12dB)
count<=0;
zhuangtai<=1;
end
else
begin
datain<=(datain<<1);
sdata<=datain[15];
count<=count+1;
end
1:if(count==16)
begin
datain<=16'b0010000000001000; //OB clamp level:32LSB
count<=0;
zhuangtai<=2;
end
else
begin
datain<=(datain<<1);
sdata<=datain[15];
count<=count+1;
end
2:if(count==16)
sdata<=0;
else
begin
datain<=(datain<<1);
sdata<=datain[15];
count<=count+1;
end
endcase
endmodule
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