代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/492094/6424184
v randomization.v
// File name: randomization.v
// Function: sync 1 inversion and randomization
module randomization(clk, start, rst, valid_in, DataIn, sync_in,
DataOut, sync_out);
parameter PacketLength = 8
www.eeworm.com/read/489853/6462779
c ad9851.c
3270303 11:42:24
void Set_Freq(unsigned long int Freqency)
{
unsigned char i,temp;
long int freq=0;
freq=(unsigned long int)(28.633*Freqency);
FQ_QD_AD9851=0;
for(i=0;i
www.eeworm.com/read/489853/6462780
c 9851.c
void Set_Freq(unsigned long int Freqency)
{
unsigned char i,temp;
long int freq=0;
freq=(unsigned long int)(28.633*Freqency);
FQ_QD_AD9851=0;
for(i=0;i
www.eeworm.com/read/486147/6544381
hier_info liid.hier_info
|liid
clk => clk~0.IN2
rst_n => rst_n~0.IN1
hsync
www.eeworm.com/read/481535/6642475
rpt fifo.sta.rpt
TimeQuest Timing Analyzer report for fifo
Wed Jun 18 16:23:04 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
---------------------
; Table of Contents ;
--------------------
www.eeworm.com/read/479816/6680128
hier_info keysch.hier_info
|keysch
key[64] => pc1:pc_1.key[64]
key[63] => pc1:pc_1.key[63]
key[62] => pc1:pc_1.key[62]
key[61] => pc1:pc_1.key[61]
key[60] => pc1:pc_1.key[60]
key[59] => pc1:pc_1.key[59]
key[58] => pc1:pc
www.eeworm.com/read/264003/11332719
hier_info vspi.hier_info
|vspi
clk => dvd2.CLK
clk => dvd_ctr[0].CLK
clk => dvd_ctr[1].CLK
clk => dvd_ctr[2].CLK
clk => dvd_ctr[3].CLK
clk => dvd_ctr[4].CLK
clk => tx_start_r1.CLK
clk => sck_r1.CLK
clk => sck_r2.CLK
www.eeworm.com/read/404203/11490411
v randomization.v
// File name: randomization.v
// Function: sync 1 inversion and randomization
module randomization(clk, start, rst, valid_in, DataIn, sync_in,
DataOut, sync_out);
parameter PacketLength = 8
www.eeworm.com/read/157920/11655889
hier_info cpld4gdf00.hier_info
|cpld4gdf00
/XFER u11:109./DS
/PS => u11:109./PS
/IOS => u11:109./IOS
/RD => inst.DATAIN
/WE => inst1.DATAIN
SWRESET => u11:109.SWRESET
/PWRONRST => u11:109./PWRONRST
www.eeworm.com/read/347114/11691857
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity max_sexp is
port(
datain : in vl_logic_vector(51 downto 0);
dataout : out vl_logic
);
end max_sexp;