vspi.hier_info

FPGA/CPLD VHDL语言实现SPI

|vspi
clk => dvd2.CLK
clk => dvd_ctr[0].CLK
clk => dvd_ctr[1].CLK
clk => dvd_ctr[2].CLK
clk => dvd_ctr[3].CLK
clk => dvd_ctr[4].CLK
clk => tx_start_r1.CLK
clk => sck_r1.CLK
clk => sck_r2.CLK
clk => sck_r3.CLK
clk => slvsel_r1.CLK
clk => slvsel_r2.CLK
clk => slvsel_r3.CLK
clk => irq_flag.CLK
clk => oflow.CLK
clk => col_flag.CLK
clk => ssel[0].CLK
clk => ssel[1].CLK
clk => ssel[2].CLK
clk => ssel[3].CLK
clk => ssel[4].CLK
clk => ssel[5].CLK
clk => ssel[6].CLK
clk => ssel[7].CLK
clk => ctl_reg[0].CLK
clk => ctl_reg[1].CLK
clk => ctl_reg[2].CLK
clk => ctl_reg[3].CLK
clk => ctl_reg[4].CLK
clk => ctl_reg[5].CLK
clk => ctl_reg[6].CLK
clk => ctl_reg[7].CLK
clk => bit_ctr[0].CLK
clk => bit_ctr[1].CLK
clk => bit_ctr[2].CLK
clk => tx_run.CLK
clk => shift_negative_edge.CLK
clk => shift_reg[0].CLK
clk => shift_reg[1].CLK
clk => shift_reg[2].CLK
clk => shift_reg[3].CLK
clk => shift_reg[4].CLK
clk => shift_reg[5].CLK
clk => shift_reg[6].CLK
clk => shift_reg[7].CLK
rst => shift_reg~16.OUTPUTSELECT
rst => shift_reg~17.OUTPUTSELECT
rst => shift_reg~18.OUTPUTSELECT
rst => shift_reg~19.OUTPUTSELECT
rst => shift_reg~20.OUTPUTSELECT
rst => shift_reg~21.OUTPUTSELECT
rst => shift_reg~22.OUTPUTSELECT
rst => shift_reg~23.OUTPUTSELECT
rst => shift_negative_edge~2.OUTPUTSELECT
rst => tx_run~2.OUTPUTSELECT
rst => bit_ctr~6.OUTPUTSELECT
rst => bit_ctr~7.OUTPUTSELECT
rst => bit_ctr~8.OUTPUTSELECT
rst => ctl_reg~8.OUTPUTSELECT
rst => ctl_reg~9.OUTPUTSELECT
rst => ctl_reg~10.OUTPUTSELECT
rst => ctl_reg~11.OUTPUTSELECT
rst => ctl_reg~12.OUTPUTSELECT
rst => ctl_reg~13.OUTPUTSELECT
rst => ctl_reg~14.OUTPUTSELECT
rst => ctl_reg~15.OUTPUTSELECT
rst => ssel~8.OUTPUTSELECT
rst => ssel~9.OUTPUTSELECT
rst => ssel~10.OUTPUTSELECT
rst => ssel~11.OUTPUTSELECT
rst => ssel~12.OUTPUTSELECT
rst => ssel~13.OUTPUTSELECT
rst => ssel~14.OUTPUTSELECT
rst => ssel~15.OUTPUTSELECT
rst => col_flag~2.OUTPUTSELECT
rst => oflow~2.OUTPUTSELECT
rst => irq_flag~2.OUTPUTSELECT
addr[0] => Mux0.IN1
addr[0] => Mux1.IN1
addr[0] => Mux2.IN1
addr[0] => Mux3.IN2
addr[0] => Mux4.IN2
addr[0] => Mux5.IN2
addr[0] => Mux6.IN1
addr[0] => Mux7.IN1
addr[0] => Equal0.IN1
addr[0] => Equal2.IN0
addr[0] => Equal3.IN1
addr[0] => Equal4.IN1
addr[1] => Mux0.IN0
addr[1] => Mux1.IN0
addr[1] => Mux2.IN0
addr[1] => Mux3.IN1
addr[1] => Mux4.IN1
addr[1] => Mux5.IN1
addr[1] => Mux6.IN0
addr[1] => Mux7.IN0
addr[1] => Equal0.IN0
addr[1] => Equal2.IN1
addr[1] => Equal3.IN0
addr[1] => Equal4.IN0
datain[0] => shift_reg~15.DATAB
datain[0] => ctl_reg~7.DATAB
datain[0] => ssel~7.DATAB
datain[1] => shift_reg~14.DATAB
datain[1] => ctl_reg~6.DATAB
datain[1] => ssel~6.DATAB
datain[2] => shift_reg~13.DATAB
datain[2] => ctl_reg~5.DATAB
datain[2] => ssel~5.DATAB
datain[3] => shift_reg~12.DATAB
datain[3] => ctl_reg~4.DATAB
datain[3] => ssel~4.DATAB
datain[4] => shift_reg~11.DATAB
datain[4] => ctl_reg~3.DATAB
datain[4] => ssel~3.DATAB
datain[5] => shift_reg~10.DATAB
datain[5] => ctl_reg~2.DATAB
datain[5] => ssel~2.DATAB
datain[5] => cf_proc~1.IN1
datain[6] => shift_reg~9.DATAB
datain[6] => ctl_reg~1.DATAB
datain[6] => ssel~1.DATAB
datain[6] => o_proc~2.IN1
datain[7] => shift_reg~8.DATAB
datain[7] => shift_negative_edge~0.DATAB
datain[7] => ctl_reg~0.DATAB
datain[7] => ssel~0.DATAB
datain[7] => elr_proc~3.IN1
dataout[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
dataout[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
dataout[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
dataout[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
write => gjr_proc~0.IN0
chip_sel => gjr_proc~0.IN1
irq <= irq~0.DB_MAX_OUTPUT_PORT_TYPE
misoe <= misoe~1.DB_MAX_OUTPUT_PORT_TYPE
misoi => shift_negative_edge_nxt~0.DATAB
misoo <= misoo~1.DB_MAX_OUTPUT_PORT_TYPE
mosie <= mosie~1.DB_MAX_OUTPUT_PORT_TYPE
mosii => shift_negative_edge_nxt~0.DATAA
mosio <= mosio~1.DB_MAX_OUTPUT_PORT_TYPE
scke <= ctl_reg[1].DB_MAX_OUTPUT_PORT_TYPE
scki => sck_r1~0.IN1
scko <= scko~0.DB_MAX_OUTPUT_PORT_TYPE
slvsele <= ctl_reg[1].DB_MAX_OUTPUT_PORT_TYPE
slvselo[0] <= ssel[0].DB_MAX_OUTPUT_PORT_TYPE
slvselo[1] <= ssel[1].DB_MAX_OUTPUT_PORT_TYPE
slvselo[2] <= ssel[2].DB_MAX_OUTPUT_PORT_TYPE
slvselo[3] <= ssel[3].DB_MAX_OUTPUT_PORT_TYPE
slvselo[4] <= ssel[4].DB_MAX_OUTPUT_PORT_TYPE
slvsel => misoe_lcl~0.IN1
slvsel => slvsel_r1.DATAIN