randomization.v

精通verilog_hdl语言编程实例程序代码

// File name:	randomization.v
// Function:	sync 1 inversion and randomization 
module randomization(clk, start, rst, valid_in, DataIn, sync_in, 
					DataOut, sync_out);
parameter PacketLength = 8'd188;
// 输入/输出端口定义
input  		 clk, start, rst, valid_in, sync_in;
input  [7:0] DataIn;
output [7:0] DataOut;
output  sync_out;

// 变量定义
reg    [7:0] DataOut;
reg 	sync_out;
reg    [7:0]  ByteCount;
reg    [3:0]  PackCount;
reg    [15:1] m_sequence;
reg    [7:0]  m_seq_reg;

always @(posedge clk or posedge rst)begin: Randomization
integer  i;
	reg [15:1] temp_seq;
	reg [7:0]  temp_reg;
	if(rst)begin
		ByteCount  <= 1;
		PackCount  <= 1;
		DataOut    <= 0; 
		m_sequence <= 15'b000_0000_0000_0000;
		m_seq_reg  <= 8'b0000_0000;
	end
	else if(valid_in) begin
		if(start)begin
			DataOut   <= ~DataIn;		// 同步字节翻转
			ByteCount <= 2;
			PackCount <= 1;
			m_sequence <= 15'b010_1001_0000_0011;	
			m_seq_reg  <= 8'b0000_0011;
		end
		else begin
			// m 序列生成器
			temp_seq = m_sequence;
			for(i=7; i>=0; i=i-1)begin
				temp_reg[i] = temp_seq[15]^temp_seq[14];
				temp_seq    = {temp_seq[14:1], temp_reg[i]};				
			end
			m_sequence <= temp_seq;
			m_seq_reg  <= temp_reg;

			case(ByteCount)
				8'h01: begin	// 每一包的第一个字节
					if(PackCount == 1)begin	// 每一帧的第一包
						DataOut   <= ~DataIn;	// 同步字节翻转
						ByteCount <= 2;
					end			
					else begin	// 每一帧的随后7个包
						DataOut   <= DataIn;	// 同步字节保持不变									ByteCount <= 2;
					end
				end 
				PacketLength: begin	
					if(PackCount==8) PackCount <= 1;
					else 			 	   PackCount <= PackCount + 1;
					ByteCount <= 1;
					DataOut <= DataIn ^ m_seq_reg;
				end
				default: begin
					ByteCount = ByteCount +1;
					DataOut <= DataIn ^ m_seq_reg;
				end
			endcase
		end

		sync_out  <= sync_in;
	end
	else begin
		{sync_out, DataOut} <= {sync_in, 8'h00};
	end
end
endmodule