liid.hier_info

利用fpga实现vga解码

|liid
clk => clk~0.IN2
rst_n => rst_n~0.IN1
hsync <= vga:vgak.hsync
vsync <= vga:vgak.vsync
vga_r <= vga:vgak.vga_r
vga_g <= vga:vgak.vga_g
vga_b <= vga:vgak.vga_b
cs1 => ~NO_FANOUT~
cs2 => we_a_from_arm~0.IN0
cs4 => ~NO_FANOUT~
cs5 => ~NO_FANOUT~
oe => ~NO_FANOUT~
we => we_a_from_arm~0.IN1
data[0] => data_from_arm[0].DATAIN
data[1] => data_from_arm[1].DATAIN
data[2] => data_from_arm[2].DATAIN
data[3] => data_from_arm[3].DATAIN
data[4] => data_from_arm[4].DATAIN
data[5] => data_from_arm[5].DATAIN
data[6] => data_from_arm[6].DATAIN
data[7] => data_from_arm[7].DATAIN
addr[0] => addr_from_arm[0].DATAIN
addr[1] => addr_from_arm[1].DATAIN
addr[2] => addr_from_arm[2].DATAIN
addr[3] => addr_from_arm[3].DATAIN
addr[4] => addr_from_arm[4].DATAIN
addr[5] => addr_from_arm[5].DATAIN
addr[6] => ~NO_FANOUT~
addr[7] => ~NO_FANOUT~
addr[8] => ~NO_FANOUT~
addr[9] => ~NO_FANOUT~
addr[10] => ~NO_FANOUT~
addr[11] => ~NO_FANOUT~
addr[12] => ~NO_FANOUT~
addr[13] => ~NO_FANOUT~
addr[14] => ~NO_FANOUT~
addr[15] => ~NO_FANOUT~
keys[0] => ~NO_FANOUT~
keys[1] => ~NO_FANOUT~
keys[2] => ~NO_FANOUT~
keys[3] => ~NO_FANOUT~
high <= <VCC>


|liid|video_buffer:video_bufferk
data_a[0] => ram.data_a[0].DATAIN
data_a[0] => q_a~7.DATAB
data_a[0] => ram__dual.DATAIN
data_a[0] => ram.DATAIN
data_a[1] => ram.data_a[1].DATAIN
data_a[1] => q_a~6.DATAB
data_a[1] => ram__dual.DATAIN1
data_a[1] => ram.DATAIN1
data_a[2] => ram.data_a[2].DATAIN
data_a[2] => q_a~5.DATAB
data_a[2] => ram__dual.DATAIN2
data_a[2] => ram.DATAIN2
data_a[3] => ram.data_a[3].DATAIN
data_a[3] => q_a~4.DATAB
data_a[3] => ram__dual.DATAIN3
data_a[3] => ram.DATAIN3
data_a[4] => ram.data_a[4].DATAIN
data_a[4] => q_a~3.DATAB
data_a[4] => ram__dual.DATAIN4
data_a[4] => ram.DATAIN4
data_a[5] => ram.data_a[5].DATAIN
data_a[5] => q_a~2.DATAB
data_a[5] => ram__dual.DATAIN5
data_a[5] => ram.DATAIN5
data_a[6] => ram.data_a[6].DATAIN
data_a[6] => q_a~1.DATAB
data_a[6] => ram__dual.DATAIN6
data_a[6] => ram.DATAIN6
data_a[7] => ram.data_a[7].DATAIN
data_a[7] => q_a~0.DATAB
data_a[7] => ram__dual.DATAIN7
data_a[7] => ram.DATAIN7
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
addr_a[0] => ram.waddr_a[0].DATAIN
addr_a[0] => ram__dual.WADDR
addr_a[0] => ram.WADDR
addr_a[0] => ram.RADDR
addr_a[1] => ram.waddr_a[1].DATAIN
addr_a[1] => ram__dual.WADDR1
addr_a[1] => ram.WADDR1
addr_a[1] => ram.RADDR1
addr_a[2] => ram.waddr_a[2].DATAIN
addr_a[2] => ram__dual.WADDR2
addr_a[2] => ram.WADDR2
addr_a[2] => ram.RADDR2
addr_a[3] => ram.waddr_a[3].DATAIN
addr_a[3] => ram__dual.WADDR3
addr_a[3] => ram.WADDR3
addr_a[3] => ram.RADDR3
addr_a[4] => ram.waddr_a[4].DATAIN
addr_a[4] => ram__dual.WADDR4
addr_a[4] => ram.WADDR4
addr_a[4] => ram.RADDR4
addr_a[5] => ram.waddr_a[5].DATAIN
addr_a[5] => ram__dual.WADDR5
addr_a[5] => ram.WADDR5
addr_a[5] => ram.RADDR5
addr_a[6] => ram.waddr_a[6].DATAIN
addr_a[6] => ram__dual.WADDR6
addr_a[6] => ram.WADDR6
addr_a[6] => ram.RADDR6
addr_a[7] => ram.waddr_a[7].DATAIN
addr_a[7] => ram__dual.WADDR7
addr_a[7] => ram.WADDR7
addr_a[7] => ram.RADDR7
addr_a[8] => ~NO_FANOUT~
addr_a[9] => ~NO_FANOUT~
addr_b[0] => ram__dual.RADDR
addr_b[1] => ram__dual.RADDR1
addr_b[2] => ram__dual.RADDR2
addr_b[3] => ram__dual.RADDR3
addr_b[4] => ram__dual.RADDR4
addr_b[5] => ram__dual.RADDR5
addr_b[6] => ram__dual.RADDR6
addr_b[7] => ram__dual.RADDR7
addr_b[8] => ~NO_FANOUT~
addr_b[9] => ~NO_FANOUT~
we_a => ram.we_a.DATAIN
we_a => q_a~7.OUTPUTSELECT
we_a => q_a~6.OUTPUTSELECT
we_a => q_a~5.OUTPUTSELECT
we_a => q_a~4.OUTPUTSELECT
we_a => q_a~3.OUTPUTSELECT
we_a => q_a~2.OUTPUTSELECT
we_a => q_a~1.OUTPUTSELECT
we_a => q_a~0.OUTPUTSELECT
we_a => ram__dual.WE
we_a => ram.WE
we_b => q_b[0]~reg0.ENA
we_b => q_b[1]~reg0.ENA
we_b => q_b[2]~reg0.ENA
we_b => q_b[3]~reg0.ENA
we_b => q_b[4]~reg0.ENA
we_b => q_b[5]~reg0.ENA
we_b => q_b[6]~reg0.ENA
we_b => q_b[7]~reg0.ENA
clk => q_a[7]~reg0.CLK
clk => q_a[6]~reg0.CLK
clk => q_a[5]~reg0.CLK
clk => q_a[4]~reg0.CLK
clk => q_a[3]~reg0.CLK
clk => q_a[2]~reg0.CLK
clk => q_a[1]~reg0.CLK
clk => q_a[0]~reg0.CLK
clk => q_b[7]~reg0.CLK
clk => q_b[6]~reg0.CLK
clk => q_b[5]~reg0.CLK
clk => q_b[4]~reg0.CLK
clk => q_b[3]~reg0.CLK
clk => q_b[2]~reg0.CLK
clk => q_b[1]~reg0.CLK
clk => q_b[0]~reg0.CLK
clk => ram.data_a[0].CLK
clk => ram.data_a[1].CLK
clk => ram.data_a[2].CLK
clk => ram.data_a[3].CLK
clk => ram.data_a[4].CLK
clk => ram.data_a[5].CLK
clk => ram.data_a[6].CLK
clk => ram.data_a[7].CLK
clk => ram.waddr_a[0].CLK
clk => ram.waddr_a[1].CLK
clk => ram.waddr_a[2].CLK
clk => ram.waddr_a[3].CLK
clk => ram.waddr_a[4].CLK
clk => ram.waddr_a[5].CLK
clk => ram.waddr_a[6].CLK
clk => ram.waddr_a[7].CLK
clk => ram.we_a.CLK
clk => ram__dual.CLK0
clk => ram.CLK0
q_a[0] <= q_a[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[1] <= q_a[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[2] <= q_a[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[3] <= q_a[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[4] <= q_a[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[5] <= q_a[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[6] <= q_a[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_a[7] <= q_a[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[0] <= q_b[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[1] <= q_b[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[2] <= q_b[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[3] <= q_b[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[4] <= q_b[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[5] <= q_b[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[6] <= q_b[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q_b[7] <= q_b[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|liid|vga:vgak
clk => x_cnt[9].CLK
clk => x_cnt[8].CLK
clk => x_cnt[7].CLK
clk => x_cnt[6].CLK
clk => x_cnt[5].CLK
clk => x_cnt[4].CLK
clk => x_cnt[3].CLK
clk => x_cnt[2].CLK
clk => x_cnt[1].CLK
clk => x_cnt[0].CLK
clk => y_cnt[9].CLK
clk => y_cnt[8].CLK
clk => y_cnt[7].CLK
clk => y_cnt[6].CLK
clk => y_cnt[5].CLK
clk => y_cnt[4].CLK
clk => y_cnt[3].CLK
clk => y_cnt[2].CLK
clk => y_cnt[1].CLK
clk => y_cnt[0].CLK
clk => hsync_r.CLK
clk => vsync_r.CLK
rst_n => y_cnt[0].ACLR
rst_n => y_cnt[1].ACLR
rst_n => y_cnt[2].ACLR
rst_n => y_cnt[3].ACLR
rst_n => y_cnt[4].ACLR
rst_n => y_cnt[5].ACLR
rst_n => y_cnt[6].ACLR
rst_n => y_cnt[7].ACLR
rst_n => y_cnt[8].ACLR
rst_n => y_cnt[9].ACLR
rst_n => vsync_r.ACLR
rst_n => hsync_r.ACLR
rst_n => x_cnt[9].ACLR
rst_n => x_cnt[8].ACLR
rst_n => x_cnt[7].ACLR
rst_n => x_cnt[6].ACLR
rst_n => x_cnt[5].ACLR
rst_n => x_cnt[4].ACLR
rst_n => x_cnt[3].ACLR
rst_n => x_cnt[2].ACLR
rst_n => x_cnt[1].ACLR
rst_n => x_cnt[0].ACLR
RGB[0] => concat~2.DATAB
RGB[1] => concat~1.DATAB
RGB[2] => concat~0.DATAB
Rgb_valid <= valid~2.DB_MAX_OUTPUT_PORT_TYPE
hsync <= hsync_r.DB_MAX_OUTPUT_PORT_TYPE
vsync <= vsync_r.DB_MAX_OUTPUT_PORT_TYPE
vga_r <= concat~0.DB_MAX_OUTPUT_PORT_TYPE
vga_g <= concat~1.DB_MAX_OUTPUT_PORT_TYPE
vga_b <= concat~2.DB_MAX_OUTPUT_PORT_TYPE