代码搜索：dataIn
找到约 2,888 项符合「dataIn」的源代码
代码结果 2,888
www.eeworm.com/read/439176/7715372
vhd mux6_1.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mux6_1 is
port(
sel : in std_logic_vector(2 downto 0);
clk : in std_logic;
datain : in std_logic_vector(9 downto 0);
d
www.eeworm.com/read/439096/7717043
h lcd_12864.h
//********************************** 延时子程序***************************
void delay(uint t)
{
uint i,j;
for(i=0;i
www.eeworm.com/read/199924/7814521
hier_info div20pll.hier_info
|Div20PLL
clock => clk4M.CLK
clock => reg[0].CLK
clock => reg[1].CLK
clock => reg[2].CLK
clock => reg[3].CLK
clock => reg[4].CLK
clock => phase[0].CLK
clock => phase[1].CLK
clock => pulcnt[0]
www.eeworm.com/read/296373/8108682
vhd hdb3.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hdb3 is
port(reset,clk,datain:in std_logic;
dout: out std_logic_vector(1 downto 0));
end;
architectur
www.eeworm.com/read/196115/8114523
vhd dataoutmux.vhd
--****************************************************************************************************
-- Data out register for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 04.12.2002
--**
www.eeworm.com/read/196115/8114663
vhd resltbitmask.vhd
--****************************************************************************************************
-- This module cleares/sets bit 0 and clears 1 of ALU bus for ARM7TDMI-S processor
-- Designed
www.eeworm.com/read/296029/8127437
hier_info sram.hier_info
|sram
rd => Write~0.IN1
rd => Read~0.IN1
wr => Read~1.IN0
wr => sram.we.OUTPUTSELECT
cs => Write~0.IN0
cs => Read~0.IN0
adr[0] => sram.RADDR
adr[0] => sram.WADDR
adr[1] => sram.RADDR1
adr[1]
www.eeworm.com/read/246102/12756379
hier_info div.hier_info
|div
q touch:inst4.reset
clk => touch:inst4.clk
out2
www.eeworm.com/read/141583/12996914
v data_port.v
/*********************************************************
MODULE: Sub Level SDRAM Controller Data Port Block
FILE NAME: data_port.v
VERSION: 1.0
DATE: April 8nd, 2002
AUTHOR: Hossein A